As opposed to planar complementary metal-oxide-semiconductor (CMOS) devices, vertical field effect transistors (VFETs) are oriented with a vertical fin channel disposed on a bottom source/drain and a top source/drain disposed on the fin channel. The gate runs vertically alongside the vertical fin channel. Thus, with VFETs the gate length (Lg) is decoupled from the device footprint, and as such VFETs have been pursued as a potential device option for scaling CMOS to the 5 nanometer (nm) node and beyond.
A reduction in chip power consumption can be realized by increasing the gate length (Lg) of transistors (as compared to nominal transistors) along non-critical paths on the chip as this reduces off current leakage. With conventional lateral FETs, the gate length can simply be increased (e.g., from about 2 nanometers (nm) to about 10 nm longer than nominal FETs) to increase threshold voltage (Vt) by about 20 millivolt (mV). However, in VFET architecture it is very difficult to vary fin height to achieve a different Lg relative to nominal VFETs on the same wafer.
Thus, techniques for achieving different Lg with VFET devices having the same fin height would be desirable.